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Disambiguation of "Shinohara, Hirofumi"

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A 2.17-pJ/b 5b-Response Attack-Resistant Strong PUF with Enhanced Statistical Performance.

, , , , and . ESSCIRC, page 513-516. IEEE, (2022)

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Kenichi Shinohara

Hirofumi Ishihara

Hirofumi Hosokawa

Hirofumi Kumazawa

Hirofumi Ueda

 

Other publications of authors with the same name

60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations., , , , , and . ESSCIRC, page 317-320. IEEE, (2012)A 2.17-pJ/b 5b-Response Attack-Resistant Strong PUF with Enhanced Statistical Performance., , , , and . ESSCIRC, page 513-516. IEEE, (2022)A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture., , and . ICCD, page 202-205. IEEE Computer Society, (1993)A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology., , , , , , , , , and 15 other author(s). COOL Chips, page 1-3. IEEE Computer Society, (2014)A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations., , , , , , , , , and 6 other author(s). ISSCC, page 326-606. IEEE, (2007)Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling., , , , , , and . DAC, page 884-889. ACM, (2008)Variation-aware subthreshold logic circuit design., , , , , and . ASICON, page 1-4. IEEE, (2013)A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die., , , , , , , , , and 7 other author(s). ISSCC, page 488-617. IEEE, (2007)On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect., , , , and . ESSCIRC, page 258-261. IEEE, (2008)A 100-Bit-Output Modeling Attack-Resistant SPN Strong PUF with Uniform and High-Randomness Response., , , , and . CICC, page 1-2. IEEE, (2023)