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A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration.

B. Wu, P. Dai, Y. Cheng, Y. Wang, J. Yang, Z. Wang, D. Liu, and W. Zhao. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (4): 803-815 (2020)

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Yuanqing Gao

Yuanqing Guo

Cheng-Yung Cheng

I-Fen Cheng

Ying Min Cheng

Other publications of authors with the same name

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization.R. Chen, L. Chen, J. Liang, Y. Cheng, S. Elloumi, J. Lee, K. Xu, V. Georgiev, K. Ni, P. Debacker and 2 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 30 (4): 440-448 (2022)Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength.W. Wang, V. Pavlidis, and Y. Cheng. ACM Great Lakes Symposium on VLSI, page 399-404. ACM, (2020)AES design improvement towards information safety.L. Wu, X. Wang, X. Zhao, Y. Cheng, D. Su, A. Chen, Q. Shi, and M. Tehranipoor. ISCAS, page 1706-1709. IEEE, (2016)OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits.Y. Liu, G. Dai, Y. Cheng, W. Kang, and W. Xing. ICCAD, page 1-9. IEEE, (2023)PDG: A Prefetcher for Dynamic Graph Updating.X. Zhang, C. Liu, J. Ni, Y. Cheng, L. Zhang, H. Li, and X. Li. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (4): 1246-1259 (April 2024)A body-biasing of readout circuit for STT-RAM with improved thermal reliability.L. Yang, Y. Cheng, Y. Wang, H. Yu, W. Zhao, and A. Todri-Sanial. ISCAS, page 1530-1533. IEEE, (2015)NEAR: A Novel Energy Aware Replacement Policy for STT-MRAM LLCs.C. Liu, Y. Cheng, Y. Wang, Y. Zhang, and W. Zhao. ISCAS, page 1-5. IEEE, (2018)Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint.Y. Zhao, J. Yang, W. Zhao, A. Todri-Sanial, and Y. Cheng. J. Comput. Sci. Technol., 33 (5): 966-983 (2018)STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator.L. Song, Y. Wang, Y. Han, H. Li, Y. Cheng, and X. Li. IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1285-1296 (2017)SIP: Boosting Up Graph Computing by Separating the Irregular Property Data.J. Ni, X. Guo, and Y. Cheng. ACM Great Lakes Symposium on VLSI, page 15-20. ACM, (2020)

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Disambiguation of "Cheng, Yuanqing"

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URL
DOI
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A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration.

Please choose a person to relate this publication to

Yuanqing Gao

Yuanqing Guo

Cheng-Yung Cheng

I-Fen Cheng

Ying Min Cheng

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cheng, Yuanqing"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration.

Please choose a person to relate this publication to

Yuanqing Gao

Yuanqing Guo

Cheng-Yung Cheng

I-Fen Cheng

Ying Min Cheng

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration.