( en | de | ru )

 

Disambiguation of "Kang, Jin-Ku"

Author of the publication

copydeleteadd this publication to your clipboard
A Link Layer Design for DisplayPort Interface with State Machine Based Packet Processing.

, , , , , , and . J. Signal Process. Syst., 79 (1): 89-98 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jin Kang

Ton-Ku Kang

Ton-Ku Kang

Ton-Ku Kang

Ton-Ku Kang

 

Other publications of authors with the same name

A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier., , , , and . ISOCC, page 143-144. IEEE, (2018)A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS., , , , and . IEICE Electron. Express, 11 (17): 20140671 (2014)A low jitter clock and data recovery with a single edge sensing Bang-Bang PD., , , and . IEICE Electron. Express, 11 (7): 20140088 (2014)A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement., , , , and . ESSCIRC, page 351-354. IEEE, (2011)A PAM-4 Receiver with Selective Reference Voltage Adaptation for Low Sensitivity to Sampler Voltage Variations., and . ISOCC, page 205-206. IEEE, (2023)Fast, Efficient and Lightweight Compressed Image Super-Resolution Network for Edge Devices., , and . AICAS, page 352-356. IEEE, (2024)A 60 to 200MHz SSCG with approximate Hershey-Kiss modulation profile in 0.11µm CMOS., , , , , and . ISOCC, page 423-426. IEEE, (2012)Way-lookup buffer for low-power set-associative cache., , and . IEICE Electron. Express, 8 (23): 1961-1966 (2011)A CMOS high-speed data recovery circuit using the matched delay sampling technique., , and . IEEE J. Solid State Circuits, 32 (10): 1588-1596 (1997)Two-step Time-to-Digital Converter using pulse-shifting time-difference repetition circuit., , and . ISOCC, page 333-334. IEEE, (2021)