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JIT trace-based verification for high-level synthesis.

, , , , , и . FPT, стр. 228-231. IEEE, (2015)

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Kyle Simek

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Kyle Krafka

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Kyle Jamieson

 

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AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS., , , и . FCCM, стр. 127-130. IEEE Computer Society, (2016)Integrated CUDA-to-FPGA Synthesis with Network-on-Chip., , , , , и . FCCM, стр. 21-24. IEEE Computer Society, (2014)Dynamic Binding and Scheduling of Firm-Deadline Tasks on Heterogeneous Compute Resources., , , и . RTCSA, стр. 275-280. IEEE Computer Society, (2010)Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation., , , , , и . DAC, стр. 7:1-7:6. ACM, (2016)High-level synthesis with behavioral level multi-cycle path analysis., , , , и . FPL, стр. 1-8. IEEE, (2013)Behavioral-level IP integration in high-level synthesis., , , и . FPT, стр. 172-175. IEEE, (2015)An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization., , , и . IPDPS, стр. 83-94. IEEE Computer Society, (2012)SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems., , , , , , , , , и 2 other автор(ы). MLSys, mlsys.org, (2020)Fast and effective placement and routing directed high-level synthesis for FPGAs., , , и . FPGA, стр. 1-10. ACM, (2014)Register and thread structure optimization for GPUs., , , и . ASP-DAC, стр. 461-466. IEEE, (2013)