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Disambiguation of "Gurumani, Swathi T."

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Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation.

, , , , , and . DAC, page 7:1-7:6. ACM, (2016)

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T Attin

T Neumann

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T Hollemann

T Fauster

 

Other publications of authors with the same name

FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2220-2233 (2016)Fast and effective placement and routing directed high-level synthesis for FPGAs., , , and . FPGA, page 1-10. ACM, (2014)High-level synthesis of multiple dependent CUDA kernels on FPGA., , , , and . ASP-DAC, page 305-312. IEEE, (2013)Integrated CUDA-to-FPGA Synthesis with Network-on-Chip., , , , , and . FCCM, page 21-24. IEEE Computer Society, (2014)AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS., , , and . FCCM, page 127-130. IEEE Computer Society, (2016)Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation., , , , , and . DAC, page 7:1-7:6. ACM, (2016)High-level synthesis with behavioral level multi-cycle path analysis., , , , and . FPL, page 1-8. IEEE, (2013)Behavioral-level IP integration in high-level synthesis., , , and . FPT, page 172-175. IEEE, (2015)Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only)., , , , and . FPGA, page 278. ACM, (2016)FCUDA-SoC: Platform Integration for Field-Programmable SoC with the CUDA-to-FPGA Compiler., , , and . FPGA, page 5-14. ACM, (2016)