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CMOS design of the tree arbiter element.

, and . IEEE Trans. Very Large Scale Integr. Syst., 4 (4): 472-476 (1996)

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Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis., and . DAC, page 830-833. ACM, (2004)CMOS design of the tree arbiter element., and . IEEE Trans. Very Large Scale Integr. Syst., 4 (4): 472-476 (1996)User-Controlled, Auditable, Cross-Jurisdiction Sharing of Healthcare Data Mediated by a Public Blockchain., , , and . TrustCom, page 87-96. IEEE, (2020)A Theory of Synchrony and Asynchrony., , and . Programming Concepts and Methods, page 459-478. North-Holland, (1990)Delay-Insensitive Interface Specification and Synthesis., and . DATE, page 169-173. IEEE Computer Society / ACM, (2000)Sequencer circuits for VLSI programming., and . ASYNC, page 82-90. IEEE Computer Society, (1995)Gate-level modelling and verification of asynchronous circuits using CSPM and FDR.. ASYNC, page 83-94. IEEE Computer Society, (2007)Optimal Two-Level Delay - Insensitive Implementation of Logic Functions., and . PATMOS, volume 2451 of Lecture Notes in Computer Science, page 92-100. Springer, (2002)Models for Data-Flow Sequential Processes.. 25 Years Communicating Sequential Processes, volume 3525 of Lecture Notes in Computer Science, page 85-97. Springer, (2004)Formal design of an asynchronous DSP counterflow pipeline: a case study in handshake algebra., , , and . ASYNC, page 206-215. IEEE, (1994)