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Disambiguation of "Chuang, Ching-Te"

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Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation.

, , and . SoCC, page 105-109. IEEE, (2013)

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Shih-Te Chuang

Ching-yao Chuang

Ching-Ho Chuang

Wilhelm Ching

Paisal Chingduang

 

Other publications of authors with the same name

Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications., , , , , , , , , and . BioCAS, page 238-241. IEEE, (2013)An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer., , , , , , , , , and 7 other author(s). ISCAS, page 1-4. IEEE, (2017)A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance., , , , , , and . ESSDERC, page 157-160. IEEE, (2012)A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry., , , and . ISCAS, page 381-384. IEEE, (2009)A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist., , , , , , , , , and 9 other author(s). ISCAS, page 1468-1471. IEEE, (2013)8T single-ended sub-threshold SRAM with cross-point data-aware write operation., , , , and . ISLPED, page 169-174. IEEE/ACM, (2011)Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation., , and . SoCC, page 105-109. IEEE, (2013)A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control., , , , , , , , , and 3 other author(s). SoCC, page 110-115. IEEE, (2013)Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells., , , and . ISCAS, page 601-604. IEEE, (2015)Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness., , , , , und . ISCAS, Seite 2325-2328. IEEE, (2015)