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Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA.

, , , and . ISED, page 21-25. IEEE, (2018)

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High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit., , , , and . ISCAS, page 3034-3037. IEEE, (2013)Radix-43 based two-dimensional FFT architecture with efficient data reordering scheme., , , and . IET Comput. Digit. Tech., 13 (2): 78-86 (2019)Hardware Acceleration of SpMV Multiplier for Deep Learning., , and . VDAT, page 1-6. IEEE, (2021)Bit-Flip Attack Detection for Secure Sparse Matrix Computations on FPGA., , and . APCCAS, page 65-69. IEEE, (2023)Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering., , , , and . DTIS, page 1-2. IEEE, (2018)Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA., , , and . ISED, page 21-25. IEEE, (2018)A Hardware Accelerator for Convolutional Neural Network Using Fast Fourier Transform., , , and . VDAT, volume 892 of Communications in Computer and Information Science, page 28-36. Springer, (2018)UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs., , , and . VLSID, page 209-214. IEEE, (2019)Approximate CNN on FPGA Using Toom-Cook Multiplier., , , and . iSES, page 271-276. IEEE, (2023)Adiabatic Physical Unclonable Function Using Cross-Coupled Pair., , , and . iSES, page 278-282. IEEE, (2022)