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Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration., , , , и . APCCAS, стр. 61-64. IEEE, (2008)Analyzing Gate-Driven Circuit Parameters for Adding ESD Performances., , , , , , , , , и . ICCE-TW, стр. 1-2. IEEE, (2019)Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection., , , , , , , , и . ECCTD, стр. 1-4. IEEE, (2015)Improvement on ESD Robustness of Lateral DMOS in High-voltage CMOS ICs by Body Current Injection., , , , и . ISCAS, стр. 385-388. IEEE, (2009)Bipolar Transistors' Holding Phenomena., , , , , , , , , и 3 other автор(ы). ICCE-Taiwan, стр. 221-222. IEEE, (2023)Transmission Line Pulse Width Impacting on Device Performances., , , , , , , , , и 3 other автор(ы). ICCE-Taiwan, стр. 227-228. IEEE, (2023)Gate Voltages Impacting on Latch-up Measurements., , , , , , , , , и 2 other автор(ы). ICCE-TW, стр. 75-76. IEEE, (2022)Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection., , , , , , , , , и 1 other автор(ы). IRPS, стр. 2. IEEE, (2022)