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Memory-reduced MAP decoding for double-binary convolutional Turbo code., , и . ISCAS, стр. 469-472. IEEE, (2010)Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes., и . ISCAS (6), стр. 5786-5789. IEEE, (2005)FACCU: Enable Fast Accumulation for High-Speed DSP Systems., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 69 (12): 4634-4638 (2022)Hardware Accelerator Design for Sparse DNN Inference and Training: A Tutorial., , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 71 (3): 1708-1714 (марта 2024)Design Light-weight 3D Convolutional Networks for Video Recognition Temporal Residual, Fully Separable Block, and Fast Algorithm., , и . CoRR, (2019)An Adaptive Chase-Pyndiah Algorithm for Turbo Product Codes., , , и . IEEE Commun. Lett., 27 (4): 1065-1069 (апреля 2023)A Precision-Scalable Energy-Efficient Convolutional Neural Network Accelerator., , и . IEEE Trans. Circuits Syst., 67-I (10): 3484-3497 (2020)Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 27 (9): 2156-2169 (2019)A lightweight face detector by integrating the convolutional neural network with the image pyramid., , , и . Pattern Recognit. Lett., (2020)A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA., , , и . ISVLSI, стр. 144-149. IEEE, (2021)