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Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications.

, и . CODES+ISSS, стр. 294-299. ACM, (2006)

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Katja Ilyashava

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Maxim Ilyasov

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Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (8): 1439-1452 (2008)Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (3): 461-465 (2009)Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications., и . CODES+ISSS, стр. 294-299. ACM, (2006)Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 17 (9): 1343-1347 (2009)Data Reuse Driven Memory and Network-On-Chip Co-Synthesis., и . IESS, том 231 из IFIP Advances in Information and Communication Technology, стр. 299-312. Springer, (2007)Compiler driven data layout optimization for regular/irregular array access patterns., , , , , и . LCTES, стр. 41-50. ACM, (2008)Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints., , , , , , и . DATE, стр. 168-175. IEEE Computer Society, (2002)Compilation techniques for energy reduction in horizontally partitioned cache architectures., , и . CASES, стр. 90-96. ACM, (2005)Mitigating soft error failures for multimedia applications by selective data protection., , , , и . CASES, стр. 411-420. ACM, (2006)Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies., , , и . DAC, стр. 49-52. ACM, (2006)