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Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (8): 1439-1452 (2008)

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Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (8): 1439-1452 (2008)Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications., and . CODES+ISSS, page 294-299. ACM, (2006)Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (3): 461-465 (2009)Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (9): 1343-1347 (2009)Data Reuse Driven Memory and Network-On-Chip Co-Synthesis., and . IESS, volume 231 of IFIP Advances in Information and Communication Technology, page 299-312. Springer, (2007)Compiler driven data layout optimization for regular/irregular array access patterns., , , , , and . LCTES, page 41-50. ACM, (2008)Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints., , , , , , and . DATE, page 168-175. IEEE Computer Society, (2002)Compilation techniques for energy reduction in horizontally partitioned cache architectures., , and . CASES, page 90-96. ACM, (2005)Mitigating soft error failures for multimedia applications by selective data protection., , , , and . CASES, page 411-420. ACM, (2006)Software controlled memory layout reorganization for irregular array access patterns., , , , and . CASES, page 179-188. ACM, (2007)