Author of the publication

Design of Ultracompact Content Addressable Memory Exploiting 1T-1MTJ Cell.

, , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (5): 1450-1462 (May 2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 192-205 (2016)Task-independent auditory probes reveal changes in mental workload during simulated quadrotor UAV training., , , , , and . Health Inf. Sci. Syst., 11 (1): 12 (December 2023)Regularization-Free Structural Pruning for GPU Inference Acceleration., , , , , , , and . ISQED, page 149-153. IEEE, (2021)Design and Implementation of a Special Operator for Neural Networks Based on Noise Reduction and Super Resolution., , , , and . ASICON, page 1-4. IEEE, (2023)MTJ variation monitor-assisted adaptive MRAM write., , , , , and . DAC, page 169:1-169:6. ACM, (2016)Adaptive MRAM Write and Read with MTJ Variation Monitor., , , , , and . IEEE Trans. Emerg. Top. Comput., 9 (1): 402-413 (2021)Design of Ultracompact Content Addressable Memory Exploiting 1T-1MTJ Cell., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (5): 1450-1462 (May 2023)PROCEED: A pareto optimization-based circuit-level evaluator for emerging devices., , , and . ASP-DAC, page 818-824. IEEE, (2014)Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing., , , , , , , and . DATE, page 1438-1443. IEEE, (2017)