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Disambiguation of "Morin-Allory, Katell"

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Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism.

, , , , , , , , and . VLSI-SoC, page 1-6. IEEE, (2021)

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Katell Morin-Allory

Gabriel Morin

Dieter Morin

Helga Morin

Rudy Morin

 

Other publications of authors with the same name

Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism., , , , , , , , and . VLSI-SoC, page 1-6. IEEE, (2021)A Generic CDC Modeling for Data Stability Verification., , , and . ICECS, page 1-4. IEEE, (2023)Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems., , , , , , , , and . DDECS, page 1-4. IEEE, (2020)FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method., , and . ISVLSI, page 170-175. IEEE, (2021)From High-Level Synthesis to Bundled-Data Circuits., , , and . SAMOS, volume 12471 of Lecture Notes in Computer Science, page 200-212. Springer, (2020)A High-Level Design Flow for Locally Body Biased Asynchronous Circuits., , and . VLSI-SoC, page 1-6. IEEE, (2021)A Distributed Body-Biasing Strategy for Asynchronous Circuits., , , , , , , , and . VLSI-SoC, page 27-32. IEEE, (2019)Formal Temporal Characterization of Register Vulnerability in Digital Circuits., , , and . ISVLSI, page 1-6. IEEE, (2023)Method for Data-Driven Pruning in Micropipeline Circuits., , , , , and . VLSI-SoC, page 1-6. IEEE, (2023)Comparison of Synchronous and Asynchronous FIR Filter Architectures., , , , and . EBCCSP, page 1-8. IEEE, (2019)