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Disambiguation of "Pande, Partha Pratim"

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Energy-efficient multicore chip design through cross-layer approach.

, , , , and . DATE, page 725-730. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Partha Pratim Chakrabarti

Partha Pratim Jana

Partha Pratim Das

Partha Sampathkumaran

Amit Pande

 

Other publications of authors with the same name

DVFS-enabled sustainable wireless NoC architecture., , and . SoCC, page 301-306. IEEE, (2012)An energy-efficient millimeter-wave wireless NoC with congestion-aware routing and DVFS., , , , and . NOCS, page 192-193. IEEE, (2014)Novel interconnect infrastructures for massive multicore chips - an overview., , , , and . ISCAS, page 2777-2780. IEEE, (2008)AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3-D Architecture., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (5): 971-984 (2021)An Energy-aware Online Learning Framework for Resource Management in Heterogeneous Platforms., , , , and . ACM Trans. Design Autom. Electr. Syst., 25 (3): 28:1-28:26 (2020)Sustainable and Reliable On-Chip Wireless Communication Infrastructure for Massive Multi-core Systems., , , and . Evolutionary Based Solutions for Green Computing, volume 432 of Studies in Computational Intelligence, Springer, (2013)Abetting Planned Obsolescence by Aging 3D Networks-on-Chip., , , , , and . NOCS, page 10:1-10:8. IEEE, (2018)Enhancing performance of wireless NoCs with distributed MAC protocols., , and . ISQED, page 406-411. IEEE, (2015)A Dual-Output Step-Down Switched-Capacitor Voltage Regulator With a Flying Capacitor Crossing Technique for Enhanced Power Efficiency., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (12): 2861-2871 (2019)High-throughput, energy-efficient network-on-chip-based hardware accelerators., , and . Sustain. Comput. Informatics Syst., 3 (1): 36-46 (2013)