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Novel interconnect infrastructures for massive multicore chips - an overview.

, , , , and . ISCAS, page 2777-2780. IEEE, (2008)

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Intra-chip Wireless Interconnect: The Road Ahead., , , , , , and . NoCArc@MICRO, page 3:1-3:6. ACM, (2017)An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links., , and . NOCS, page 2:1-2:8. ACM, (2015)W1B: Application specific designs.. SoCC, page 1. IEEE, (2017)A One-to-Many Traffic Aware Wireless Network-in-Package for Multi-Chip Computing Platforms., , , , and . SoCC, page 284-289. IEEE, (2018)Energy-efficient multicore chip design through cross-layer approach., , , , and . DATE, page 725-730. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Design Space Exploration for Wireless NoCs Incorporating Irregular Network Routing., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (11): 1732-1745 (2014)What Can Ail Thee: New and Old Security Vulnerabilities of Wireless Datacenters., , , , and . GLOBECOM, page 1-7. IEEE, (2020)Implementation and Evaluation of Deep Neural Networks in Commercially Available Processing in Memory Hardware., , , , and . SOCC, page 1-6. IEEE, (2022)The IANET Hardware Accelerator for Audio and Visual Data Classification., , , and . SoCC, page 48-53. IEEE, (2020)Flexible Instruction Set Architecture for Programmable Look-up Table based Processing-in-Memory., , , and . ICCD, page 66-73. IEEE, (2021)