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Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.

M. Gupta, P. Weckx, S. Cosemans, P. Schuddinck, R. Baert, D. Yakimets, D. Jang, Y. Sherazi, P. Raghavan, A. Spessot, A. Mocuta, and W. Dehaene. ESSDERC, page 256-259. IEEE, (2017)

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Alessio Langiu

Alessio Meneghetti

Alessio Guerri

Alessio Quaglino

Alessio Vascon

Other publications of authors with the same name

Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery.J. Bastos, B. O'Sullivan, J. Franco, S. Tyaginov, B. Truijen, A. Chasin, R. Degraeve, B. Kaczer, R. Ritzenthaler, E. Capogreco and 7 other author(s). IRPS, page 1-6. IEEE, (2022)Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations.A. Spessot, S. Salahuddin, R. Escobar, R. Ritzenthaler, Y. Xiang, R. Budhwani, E. Litta, E. Capogreco, J. Bastos, Y. Chen and 1 other author(s). IMW, page 1-4. IEEE, (2022)Reliability impact of advanced doping techniques for DRAM peripheral MOSFETs.A. Spessot, R. Ritzenthaler, T. Schram, M. Aoulaiche, M. Cho, M. Toledano-Luque, N. Horiguchi, and P. Fazan. ICICDT, page 1-4. IEEE, (2015)Side and Corner Region Non-Uniformities in Grown SiO2 and Their Implications on Current, Capacitance and Breakdown Characteristics.J. Bastos, B. O'Sullivan, Y. Higashi, A. Chasin, J. Franco, H. Arimura, J. Ganguly, E. Capogreco, A. Spessot, and N. Horiguchi. IRPS, page 36. IEEE, (2024)Impact of Off State Stress on advanced high-K metal gate NMOSFETs.A. Spessot, M. Aoulaiche, M. Cho, J. Franco, T. Schram, R. Ritzenthaler, and B. Kaczer. ESSDERC, page 365-368. IEEE, (2014)Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.B. O'Sullivan, R. Ritzenthaler, G. Rzepa, Z. Wu, E. Litta, O. Richard, T. Conard, V. Machkaoutsan, P. Fazan, C. Kim and 6 other author(s). IRPS, page 1-8. IEEE, (2019)I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration.R. Ritzenthaler, T. Schram, M. Cho, A. Mocuta, N. Horiguchi, A. Thean, A. Spessot, C. Caillat, M. Aoulaiche, P. Fazan and 2 other author(s). ICICDT, page 1-4. IEEE, (2015)Dedicated technology threshold voltage tuning for 6T SRAM beyond N7.M. Gupta, P. Weckx, S. Cosemans, P. Schuddinck, R. Baert, D. Jang, Y. Sherazi, P. Raghavan, A. Spessot, A. Mocuta and 1 other author(s). ICICDT, page 1-4. IEEE, (2017)Assessment of SiGe quantum well transistors for DRAM peripheral applications.R. Ritzenthaler, T. Schram, G. Eneman, A. Mocuta, N. Horiguchi, A. Thean, A. Spessot, M. Aoulaiche, P. Fazan, K. Noh and 1 other author(s). ICICDT, page 1-4. IEEE, (2015)Off-state stress degradation mechanism on advanced p-MOSFETs.M. Cho, A. Spessot, B. Kaczer, M. Aoulaiche, R. Ritzenthaler, T. Schram, P. Fazan, N. Horiguchi, and D. Linten. ICICDT, page 1-4. IEEE, (2015)

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Disambiguation of "Spessot, Alessio"

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Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.

Please choose a person to relate this publication to

Alessio Langiu

Alessio Meneghetti

Alessio Guerri

Alessio Quaglino

Alessio Vascon

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Spessot, Alessio"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.

Please choose a person to relate this publication to

Alessio Langiu

Alessio Meneghetti

Alessio Guerri

Alessio Quaglino

Alessio Vascon

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.