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Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors.

, , , , , and . FCCM, page 202. IEEE, (2023)

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Performance impacts and limitations of hardware memory access trace collection., , , , and . DATE, page 506-511. IEEE, (2017)A configurable framework for investigating workload execution., , and . FPT, page 409-412. IEEE, (2010)Evaluating the Performance Efficiency of a Soft-Processor, Variable-Length, Parallel-Execution-Unit Architecture for FPGAs Using the RISC-V ISA., , and . FCCM, page 1-8. IEEE Computer Society, (2018)Polyblaze: From one to many bringing the microblaze into the multicore era with Linux SMP support., , and . FPL, page 224-230. IEEE, (2012)TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features., and . FPL, page 1-4. IEEE, (2017)Exploring Writeback Designs for Efficiently Leveraging Parallel-Execution Units in FPGA-Based Soft-Processors., , and . FCCM, page 120-128. IEEE, (2020)Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors., , , , , and . FCCM, page 202. IEEE, (2023)Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy., , , , , and . MICRO, page 376-388. IEEE Computer Society, (2012)A Demonstration of a Natural Language Query Interface to an Event-Based Semantic Web Triplestore., , , , and . ESWC (Satellite Events), volume 8798 of Lecture Notes in Computer Science, page 343-348. Springer, (2014)Rethinking Integer Divider Design for FPGA-Based Soft-Processors., , , and . FCCM, page 289-297. IEEE, (2019)