Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique.

W. Deng, D. Yang, T. Ueno, T. Siriburanon, S. Kondo, K. Okada, and A. Matsuzawa. ISSCC, page 266-267. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Wei Wei

Other publications of authors with the same name

Automatic model redundancy reduction for fast back-propagation for deep neural networks in speech recognition.Y. Qian, T. He, W. Deng, and K. Yu. IJCNN, page 1-6. IEEE, (2015)A 27-to-31.6 GHz 8-Element Phased-Array Transmitter Front-End with Inter-Element-Interference Cancellation Scheme in 65 nm CMOS.D. Li, W. Deng, X. Li, R. Qiu, H. Jia, X. Huang, Z. Guo, and B. Chi. A-SSCC, page 1-3. IEEE, (2023)Non-convex Learning via Replica Exchange Stochastic Gradient MCMC.W. Deng, Q. Feng, L. Gao, F. Liang, and G. Lin. ICML, volume 119 of Proceedings of Machine Learning Research, page 2474-2483. PMLR, (2020)Find Intelligent Knowledge by Second-Order Mining: Three Cases from China.G. Nie, L. Zhang, Y. Zhang, W. Deng, and Y. Shi. ICDM Workshops, page 1189-1195. IEEE Computer Society, (2010)Application of Object-Oriented Analysis and Design in CDMA BSS Development.W. Ye, Y. Du, and W. Deng. TOOLS (36), page 73-80. IEEE Computer Society, (2000)An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB.D. Yang, W. Deng, B. Liu, T. Siriburanon, K. Okada, and A. Matsuzawa. ESSCIRC, page 197-200. IEEE, (2016)A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB.A. Narayanan, M. Katsuragi, K. Kimura, S. Kondo, K. Tokgoz, K. Nakata, W. Deng, K. Okada, and A. Matsuzawa. ESSCIRC, page 380-383. IEEE, (2015)A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS.H. Liu, Z. Sun, H. Huang, W. Deng, T. Siriburanon, J. Pang, Y. Wang, R. Wu, T. Someya, A. Shirane and 1 other author(s). ISSCC, page 256-258. IEEE, (2019)Quantum Key Supply and Dynamic Adjustment Strategy for Power Dispatch.W. Deng, Z. Yu, Y. Zhang, L. Yi, and Y. Ma. ICSAI, page 812-817. IEEE, (2018)An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation.W. Deng, K. Okada, and A. Matsuzawa. ASP-DAC, page 103-104. IEEE, (2011)

BibSonomy

Disambiguation of "Deng, Wei"

Please choose a person to relate this publication to

Wei Wei

Wei Wei

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Deng, Wei"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique.

Please choose a person to relate this publication to

Wei Wei

Wei Wei

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation