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SPREX: A soft processor with Runahead execution., and . ReConFig, page 1-7. IEEE, (2012)A dual grain hit-miss detector for large die-stacked DRAM caches., , , , , and . DATE, page 89-92. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Optimizing Memory Translation Emulation in Full System Emulators., , , and . ACM Trans. Archit. Code Optim., 11 (4): 60:1-60:24 (2014)Dynamic Stripes: Exploiting the Dynamic Precision Requirements of Activation Values in Neural Networks., , , and . CoRR, (2017)Reducing OLTP instruction misses with thread migration., , , and . DaMoN, page 9-15. ACM, (2012)A physical level study and optimization of CAM-based checkpointed register alias table., , and . ISLPED, page 233-236. ACM, (2008)On the latency, energy and area of checkpointed, superscalar register alias tables., , , , and . ISLPED, page 379-382. ACM, (2007)cuSCNN : an Efficient CUDA Implementation of Sparse CNNs., , , , and . HEART, page 107-113. ACM, (2023)Mokey: enabling narrow fixed-point inference for out-of-the-box floating-point transformer models., , , and . ISCA, page 888-901. ACM, (2022)Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors., and . HPCA, page 301-312. IEEE Computer Society, (2000)