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Efficient and High-Speed CGRA Accelerator for Cryptographic Applications.

, , , , and . candar, page 189-195. IEEE, (2023)

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A Multi-Mode Error-Correction Solution Based on Split-Concatenation for Wireless Sensor Nodes., , and . J. Commun., 12 (2): 130-136 (2017)Hardware Design of Multi Gbps RC4 Stream Cipher., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (11): 2120-2127 (2013)A design of low complex log likelihood ratio for MIMO decoder using the bit shift., , , , and . APCCAS, page 727-730. IEEE, (2014)Hardware Implementation of High Throughput RC4 algorithm., , , , and . ISCAS, page 77-80. IEEE, (2012)CSIP: A Compact Scrypt IP design with single PBKDF2 core for Blockchain mining., , , and . SBCCI, page 1-6. IEEE, (2022)Efficient and High-Speed CGRA Accelerator for Cryptographic Applications., , , , and . candar, page 189-195. IEEE, (2023)ASIC design of 7.7 Gbps multi-mode LDPC decoder for IEEE 802.11ac., , , and . ISCIT, page 259-263. IEEE, (2014)ASIC design of MUL-RED Radix-2 Pipeline FFT circuit for 802.11ah system., , , and . COOL Chips, page 1-3. IEEE Computer Society, (2016)Run-Length Limited Decoding for Visible Light Communications: A Deep Learning Approach., , , and . APCC, page 496-501. IEEE, (2019)CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis., , , , , , and . CANDAR, page 375-380. IEEE Computer Society, (2016)