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Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA.

, , , and . DSD, page 250-257. IEEE Computer Society, (2012)

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Fault tolerant Field Programmable Neural Networks., , and . NORCAS, page 1-4. IEEE, (2015)Testability analysis based on the identification of testable blocks with predefined properties., , and . Microprocess. Microsystems, 32 (5-6): 296-302 (2008)Automated Functional Verification of Application Specific Instruction-set Processors., , , and . IESS, volume 403 of IFIP Advances in Information and Communication Technology, page 128-138. Springer, (2013)Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis., , and . EWDTS, page 1-7. IEEE, (2018)The Identification of registers in RTL Structures for the Test Application., , and . ISoLA (Preliminary proceedings), volume TR-2004-6 of Technical Report, page 317-319. Department of Computer Science, University of Cyprus, (2004)Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study., , , , , and . DSD, page 597-600. IEEE, (2019)A Probabilistic Context-Free Grammar Based Random Test Program Generation., and . DSD, page 356-359. IEEE Computer Society, (2017)Automation and Optimization of Coverage-driven Verification., and . DSD, page 87-94. IEEE Computer Society, (2015)Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA., and . DDECS, page 171-174. IEEE Computer Society, (2014)FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties., , and . DDECS, page 285-289. IEEE Computer Society, (2006)