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Disambiguation of "Kastil, Jan"

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Fault tolerant Field Programmable Neural Networks.

, , and . NORCAS, page 1-4. IEEE, (2015)

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Tsai-Yu Jansen

Einfluss der Konversion laparoskopischer Operationen auf Tumorwachstum, hepatische Metastasierung und Tumorangiogenese. Uni Heidelberg, (2010)

Dirk Jansen

Temperaturkorrektur von mit dem Falling-Weight-Deflectometer gemessenen Deflexionen auf Asphaltbefestigungen. Uni Duisburg-Essen, (2009)

Matthäus Janczyk

Synthese funktionalisierter Trinukleotide und ihre Anwendung bei der Randomisierung. Uni Greifswald, (2009)

Christoph Janello

Wertschöpfung im digitalisierten Buchmarkt. Uni München, (2010)

Richard Janissen

Biomolecular based nano-manipulation with a combined atomic force microscope and single molecule fluorescence setup. Uni Düsseldorf, (2009)
 

Other publications of authors with the same name

Fault tolerant Field Programmable Neural Networks., , and . NORCAS, page 1-4. IEEE, (2015)Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration., , and . DSD, page 365-372. IEEE Computer Society, (2010)High speed pattern matching algorithm based on deterministic finite automata with faulty transition table., and . ANCS, page 7. ACM, (2010)Mapping Trained Neural Networks to FPNNs., , and . DDECS, page 157-160. IEEE Computer Society, (2015)Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing., , and . DSD, page 823-829. IEEE Computer Society, (2009)Optimalizace algoritmů a DatovýCH Struktur Pro VyhledáVání ReguláRníCH VýRazů S VyužITíM Technologie FPGA ; Optimization of Algorithms and Data Structures for Regular expression Matching using FPGA Technology.. Brno University of Technology, Czech Republic, (2016)base-search.net (ftunivtbrno:oai:https://dspace.vut.cz:11012/63231).Hardware accelerated pattern matching based on Deterministic Finite Automata with perfect hashing., and . DDECS, page 149-152. IEEE Computer Society, (2010)Hardware architecture for the fast pattern matching., , and . DDECS, page 120-123. IEEE Computer Society, (2013)Netbench: Framework for Evaluation of Packet Processing Algorithms., , , , and . ANCS, page 95-96. IEEE Computer Society, (2011)Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA., , , and . DSD, page 250-257. IEEE Computer Society, (2012)