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Efficient techniques for 3-D impedance extraction using mixed boundary element method.

, , , , and . ASP-DAC, page 158-163. IEEE, (2008)

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Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network., , , , , and . DATE, page 1463-1468. IEEE, (2019)An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble., , , , and . CoRR, (2021)LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces., , , , and . MLCAD, page 27-34. ACM / IEEE, (2022)A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion., , , , , and . ISCAS, page 2886-2890. IEEE, (2022)Efficient High-Level Synthesis of Approximate Computing Circuits via Multi-fidelity Modeling., , , and . ASICON, page 1-4. IEEE, (2021)cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis., , , , , , , , , and . DAC, page 1-6. IEEE, (2023)Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data., , , , and . DATE, page 1417-1422. IEEE, (2016)An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits., , , , , , , and . DAC, page 1-6. IEEE, (2020)Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method., , and . ASP-DAC, page 844-849. IEEE, (2006)Layout decomposition with pairwise coloring for multiple patterning lithography., , , , and . ICCAD, page 170-177. IEEE, (2013)