From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

Exploring optimized accelerator design for binarized convolutional neural networks., , , , , и . IJCNN, стр. 2510-2516. IEEE, (2017)Logarithmic Compression for Memory Footprint Reduction in Neural Network Training., , , , , , , , и . CANDAR, стр. 291-297. IEEE Computer Society, (2017)FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting., , , , , и . ReConFig, стр. 1-6. IEEE, (2016)QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS., , , , , , и . IEEE J. Solid State Circuits, 54 (1): 186-196 (2019)A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS., , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 692-703 (2021)Accelerating deep learning by binarized hardware., , , , , , , и . APSIPA, стр. 1045-1051. IEEE, (2017)QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS., , , , , , , , и . ISSCC, стр. 216-218. IEEE, (2018)DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 1-3. IEEE, (2022)In-memory area-efficient signal streaming processor design for binary neural networks., , , , , , , , , и 1 other автор(ы). MWSCAS, стр. 116-119. IEEE, (2017)A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes., , , , , , , , и . ISCAS, стр. 1-5. IEEE, (2020)