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Adaptive Clock Gating for Improving Wear out induced Duty Cycle Shift in the Clock Network., , , and . IRPS, page 1-4. IEEE, (2024)A Unified Aging Model Framework Capturing Device to Circuit Degradation for Advance Technology Nodes., , , , , , and . IRPS, page 1-4. IEEE, (2023)Novel Re-configurable Circuits For Aging Characterization: Connecting Devices to Circuits., , , , , , , , , and . IRPS, page 1-5. IEEE, (2020)Q&R On-Chip (QROC): A Unified, Oven-less and Scalable Circuit Reliability Platform., , , , , , , , , and . IRPS, page 1-6. IEEE, (2022)Node sensitivity analysis for soft errors in CMOS logic., , , and . ITC, page 9. IEEE Computer Society, (2005)Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA., , and . DATE, page 1460-1465. EDA Consortium, San Jose, CA, USA, (2007)Combinational Logic Soft Error Correction., , , , , and . ITC, page 1-9. IEEE Computer Society, (2006)Soft Delay Error Effects in CMOS Combinational Circuits., , and . VTS, page 325-334. IEEE Computer Society, (2004)An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories., , , , and . DATE, page 592-597. IEEE Computer Society, (2005)Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM., , and . IOLTS, page 266-271. IEEE Computer Society, (2005)