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New Techniques to Reduce the Execution Time of Functional Test Programs., , , and . IEEE Trans. Computers, 66 (7): 1268-1273 (2017)An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard., , , , , and . LATS, page 1-6. IEEE, (2017)The Use of Model Checking in ATPG for Sequential Circuits., , , and . CAV, volume 531 of Lecture Notes in Computer Science, page 86-95. Springer, (1990)BASTION: Board and SoC test instrumentation for ageing and no failure found., , , , , , , , and . DATE, page 115-120. IEEE, (2017)Test-Plan Optimization for Flying-Probes In-Circuit Testers., , , and . ITC-Asia, page 19-24. IEEE, (2019)Software-Based Self-Test for Transition Faults: a Case Study., , , and . VLSI-SoC, page 76-81. IEEE, (2019)A Novel Sequence Generation Approach to Diagnose Faults in Reconfigurable Scan Networks., , , and . IEEE Trans. Computers, 69 (1): 87-98 (2020)On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors., , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (4): 813-823 (2014)New techniques for efficiently assessing reliability of SOCs., , , , and . Microelectron. J., 34 (1): 53-61 (2003)RT-Level ITC'99 Benchmarks and First ATPG Results., , and . IEEE Des. Test Comput., 17 (3): 44-53 (2000)