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Disambiguation of "De, Vivek"

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On-Die Supply-Resonance Suppression Using Band-Limited Active Damping.

, , , , , , , , , , and . ISSCC, page 286-603. IEEE, (2007)

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Nagarajavel Vivekananthan

Vivek Venkataramani

Vivek Ramamurthy

Vivek Shetty

Vivek Bose

 

Other publications of authors with the same name

On-Chip High-Resolution Timing Characterization Circuits for Memory IPs., , , , , , and . ESSCIRC, page 377-380. IEEE, (2022)A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications., , , , , , and . ESSCIRC, page 355-358. IEEE, (2005)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS., , , , , , , , , and 11 other author(s). ISSCC, page 66-68. IEEE, (2012)F1: Designing secure systems: Manufacturing, circuits and architectures., , , , , , and . ISSCC, page 492-494. IEEE, (2016)A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer., , , , , , , , and . ISSCC, page 478-480. IEEE, (2022)Circuit techniques for low-power CMOS GSI., , , and . ISLPED, page 193-196. IEEE, (1996)A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction., , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)Improving compute in-memory ECC reliability with successive correction., , , , , , , and . DAC, page 745-750. ACM, (2022)8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator., , , , , and . ISSCC, page 142-143. IEEE, (2017)Low power and high performance design challenges in future technologies., and . ACM Great Lakes Symposium on VLSI, page 1-6. ACM, (2000)