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On-Chip Interconnection Networks of the TRIPS Chip., , , , , , и . IEEE Micro, 27 (5): 41-50 (2007)Fast Sort on CPUs, GPUs and Intel MIC Architectures, , , , , , и . Technical Report, Intel Labs, (2010)Can traditional programming bridge the ninja performance gap for parallel computing applications?, , , , , , , и . Commun. ACM, 58 (5): 77-86 (2015)Distributed Microarchitectural Protocols in the TRIPS Prototype Processor., , , , , , , , , и 7 other автор(ы). MICRO, стр. 480-491. IEEE Computer Society, (2006)A NUCA substrate for flexible CMP cache sharing., , , , , и . ICS, стр. 31-40. ACM, (2005)Implementation and Evaluation of On-Chip Network Architectures., , , , и . ICCD, стр. 477-484. IEEE, (2006)ClearPath: highly parallel collision avoidance for multi-agent simulation., , , , , , и . Symposium on Computer Animation, стр. 177-187. ACM, (2009)An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches., , и . ASPLOS, стр. 211-222. ACM Press, (2002)Joint interference and user association optimization in cellular wireless networks., , и . ACSSC, стр. 511-515. IEEE, (2014)Opportunistic third-party backhaul for cellular wireless networks., , и . ACSSC, стр. 1594-1600. IEEE, (2013)