Author of the publication

A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge.

, , , , , , , , and . DATE, page 730-735. IEEE, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (9): 3619-3631 (2022)Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme., , , , , and . FPGA, page 229. ACM, (2023)An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (12): 1878-1890 (2022)Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (10): 3978-3991 (October 2023)An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing., , , , , , , , , and 3 other author(s). IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (4): 821-834 (2022)Group Vectored Absolute-Value-Subtraction Cell Array for the Efficient Acceleration of AdderNet., , , , and . AICAS, page 1-5. IEEE, (2023)A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS., , , , , , and . CICC, page 1-2. IEEE, (2024)Hardware-Friendly Stochastic and Adaptive Learning in Memristor Convolutional Neural Networks., , , , , , , , , and . Adv. Intell. Syst., 3 (9): 2100041 (2021)A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge., , , , , , , , and . DATE, page 730-735. IEEE, (2022)An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (12): 5289-5301 (December 2023)