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Disambiguation of "Huang, Mingqiang"

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Group Vectored Absolute-Value-Subtraction Cell Array for the Efficient Acceleration of AdderNet.

, , , , and . AICAS, page 1-5. IEEE, (2023)

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Josef Huang

Pa Huang

Haishi Huang

Feiqing Huang

Zhida Huang

 

Other publications of authors with the same name

A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (9): 3619-3631 (2022)Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme., , , , , and . FPGA, page 229. ACM, (2023)Group Vectored Absolute-Value-Subtraction Cell Array for the Efficient Acceleration of AdderNet., , , , and . AICAS, page 1-5. IEEE, (2023)An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing., , , , , , , , , and 3 other author(s). IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (4): 821-834 (2022)EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models., , , , , and . CoRR, (2024)A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS., , , , , , and . CICC, page 1-2. IEEE, (2024)An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (12): 1878-1890 (2022)High performance transistors based on two dimensional materials., , , and . ASICON, page 1053-1056. IEEE, (2017)Dual-Line-Systolic Array for High Performance CNN Accelerator., , , and . FCCM, page 1. IEEE, (2022)A General-Purpose and Configurable Planar Data Processor for Energy-Efficient Pooling Computation., , , , and . AICAS, page 33-36. IEEE, (2022)