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High-performance video content recognition with long-term recurrent convolutional network for FPGA.

, , , , , , , , and . FPL, page 1-4. IEEE, (2017)

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ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation., , , , , , and . HPCA, page 741-755. IEEE, (2022)FSSD: FPGA-Based Emulator for SSDs., , , , , , , and . FPL, page 101-108. IEEE, (2023)Performance-driven mapping for CPLD architectures., , , and . FPGA, page 39-47. ACM, (2001)ScaleHLS: Scalable High-Level Synthesis through MLIR., , , , , , and . CoRR, (2021)Algorithm/Accelerator Co-Design and Co-Search for Edge AI., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (7): 3064-3070 (2022)VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization., , , , , and . IEEE Trans. Computers, 70 (5): 696-710 (2021)Optimality study of resource binding with multi-Vdds., , , and . DAC, page 580-585. ACM, (2006)A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation., , , , , and . DATE, page 1789-1794. EDA Consortium San Jose, CA, USA / ACM DL, (2013)High-level synthesis with behavioral level multi-cycle path analysis., , , , and . FPL, page 1-8. IEEE, (2013)Fast large-scale optimal power flow analysis for smart grid through network reduction., and . ASP-DAC, page 373-378. IEEE, (2014)