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Disambiguation of "Chang, Meng-Fan"

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A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction.

, , , , , , and . IEEE J. Solid State Circuits, 56 (5): 1588-1596 (2021)

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Fan Chen Meng

Meng-Chang Liu

Meng Meng

Meng Meng Liang

Meng Zhang

Methods and implementations of road-network matching. TU München, (2009)
 

Other publications of authors with the same name

5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel., , , , , , , , , and 3 other author(s). ISSCC, page 110-112. IEEE, (2020)13.4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices., , , , , , , , , and 2 other author(s). ISSCC, page 224-226. IEEE, (2020)14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse., , , , , , , , , and 1 other author(s). ISSCC, page 234-236. IEEE, (2020)A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors., , , , , , , , , and 7 other author(s). ISSCC, page 494-496. IEEE, (2018)A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors., , , , , , , , , and 12 other author(s). ISSCC, page 388-390. IEEE, (2019)A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification., , , , , , , and . IEEE J. Solid State Circuits, 58 (11): 3266-3274 (November 2023)A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme., , , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 815-827 (2011)A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 59 (1): 116-127 (January 2024)A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 59 (1): 52-64 (January 2024)A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 52 (8): 2194-2207 (2017)