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Disambiguation of "Emer, Joel S."

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Efficient Processing of Deep Neural Networks: A Tutorial and Survey.

, , , and . Proc. IEEE, 105 (12): 2295-2329 (2017)

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Wolfgang Emer

Sylvia Emer

Michael Emer

Sven Emersleben

Lars Emersleben

 

Other publications of authors with the same name

Design analysis of a heterogeneous distributed system., and . ACM SIGOPS European Workshop, ACM, (1986)An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs., , and . ISPASS, page 116-118. IEEE, (2020)Unlocking Ordered Parallelism with the Swarm Architecture., , , , and . IEEE Micro, 36 (3): 105-117 (2016)Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing., , , , , , , , , and 2 other author(s). ACM Trans. Comput. Syst., (2023)Loose Loops Sink Chips., , , and . HPCA, page 299-310. IEEE Computer Society, (2002)Reducing cache misses using hardware and software page placement., , and . International Conference on Supercomputing, page 155-164. ACM, (1999)A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology., , , , , , , , , and 7 other author(s). Hot Chips Symposium, page 1-24. IEEE, (2019)DAGguise: mitigating memory timing side channels., , , , , and . ASPLOS, page 329-343. ACM, (2022)Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling (Extended Abstract)., , , , , , , , , and 1 other author(s). HOPC@SPAA, page 15-16. ACM, (2023)Accelerating RTL Simulation with Hardware-Software Co-Design., , , , , and . MICRO, page 153-166. ACM, (2023)