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18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS., , , , , , , , , и . ESSCIRC, стр. 210-213. IEEE, (2010)A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS., , , , , , и . ESSCIRC, стр. 177-180. IEEE, (2012)Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS., , , , , , , , , и 6 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2020)A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS., , , , , , , и . VLSIC, стр. 118-119. IEEE, (2012)A 350mV-900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS., , , , , , , и . VLSI Circuits, стр. 1-2. IEEE, (2016)Near-threshold voltage (NTV) design: opportunities and challenges., , , , , и . DAC, стр. 1153-1158. ACM, (2012)High-Performance On-Chip Interconnect Circuit Technologies for sub-65nm CMOS.. SoCC, стр. 324. IEEE, (2005)Active shielding of RLC global interconnects., , и . Timing Issues in the Specification and Synthesis of Digital Systems, стр. 98-104. ACM, (2002)A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS., , , , , , , , , и . IEEE J. Solid State Circuits, 52 (4): 940-949 (2017)Clock net optimization using active shielding., , и . ESSCIRC, стр. 265-268. IEEE, (2003)