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Disambiguation of "Costa, Eduardo"

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Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers.

, , , , and . ICECS, page 478-481. IEEE, (2017)

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Paulo Eduardo Miranda Costa

Luís Eduardo Vergueiro Loures Costa

José Eduardo Ferreira Costa Gardolinski

Manuel Costa

Harald Costa

 

Other publications of authors with the same name

An Ultra Low-Energy VLSI Approximate Discrete Haar Wavelet Transform for ECG Data Compression., , , , and . ICECS, page 1-4. IEEE, (2023)A New Architecture for 2's Complement Gray Encoded Array Multiplier., , and . SBCCI, page 14-19. IEEE Computer Society, (2002)A power-efficient imprecise radix-4 multiplier applied to high resolution audio processing., , , , and . ICECS, page 261-264. IEEE, (2016)Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding., , , , , , , and . ICECS, page 490-493. IEEE, (2017)Approximate adder synthesis for area- and energy-efficient FIR filters in CMOS VLSI., , and . NEWCAS, page 1-4. IEEE, (2015)New Energy-Efficient 3-2 and 4-2 Approximate Adder Compressors Topologies., , , , , and . ICECS, page 1-4. IEEE, (2023)Accuracy-, Delay- and Area-Driven Evaluation of Lower-Part Approximate Parallel Prefix Adder., , , and . ICECS, page 1-4. IEEE, (2023)Power Efficient Arithmetic Operand Encoding., , and . SBCCI, page 201-206. IEEE Computer Society, (2001)Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications., , , and . DSD, page 3-10. IEEE Computer Society, (2010)Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs., , and . PATMOS, page 169-176. IEEE, (2015)