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Disambiguation of "Chen, Poki"

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A monolithic vernier-based time-to-digital converter with dual PLLs for self-calibration.

, , and . CICC, page 321-324. IEEE, (2005)

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Arno Pokiser

Peter Pokinskyj

Chen Chen

Chen Chen

Shih Chen Chen

 

Other publications of authors with the same name

A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection., , , , , , and . IEEE Access, (2022)A wide-range and fast-locking clock synthesizer IP based on delay-locked loop., , and . ISCAS (1), page 785-788. IEEE, (2004)A high-resolution and fast-conversion time-to-digital converter., , and . ISCAS (1), page 37-40. IEEE, (2003)A monolithic vernier-based time-to-digital converter with dual PLLs for self-calibration., , and . CICC, page 321-324. IEEE, (2005)All-Digital Time-Domain Smart Temperature Sensor With an Inter-Batch Inaccuracy of -0.7~°C - +0.6~°C After One-Point Calibration., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (5): 913-920 (2011)A FPGA vernier digital-to-time converter with 3.56ps resolution and -0.23∼+0.2LSB inaccuracy., , and . CICC, page 209-212. IEEE, (2008)An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC., , and . IEEE Access, (2021)Real-Time Semantic Segmentation with Dual Encoder and Self-Attention Mechanism for Autonomous Driving., , , and . Sensors, 21 (23): 8072 (2021)High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (4): 904-913 (2020)A 1280 x 720 Micro-LED Display Driver with 10-Bit Current-Mode Pulse Width Modulation., , , , , , , , , and 1 other author(s). A-SSCC, page 1-3. IEEE, (2021)