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A wide-range and fast-locking clock synthesizer IP based on delay-locked loop.

C. Hwang, P. Chen, and H. Tsao. ISCAS (1), page 785-788. IEEE, (2004)

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Arno Pokiser

Peter Pokinskyj

Chen Chen

Shih Chen Chen

Other publications of authors with the same name

A monolithic vernier-based time-to-digital converter with dual PLLs for self-calibration.P. Chen, J. Zheng, and C. Chen. CICC, page 321-324. IEEE, (2005)A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection.P. Chen, J. Wijaya, S. Kajihara, T. Adiono, H. Chen, R. Wang, and Y. Miyake. IEEE Access, (2022)A high-resolution and fast-conversion time-to-digital converter.C. Hwang, P. Chen, and H. Tsao. ISCAS (1), page 37-40. IEEE, (2003)A wide-range and fast-locking clock synthesizer IP based on delay-locked loop.C. Hwang, P. Chen, and H. Tsao. ISCAS (1), page 785-788. IEEE, (2004)A multi-channel high precision current matching LED Driver for intelligent dimming.P. Chen, H. Liu, Y. Yang, Y. Li, and F. Budiman. ISPACS, page 174-177. IEEE, (2015)A Time-Domain SAR Smart Temperature Sensor With Curvature Compensation and a 3σ Inaccuracy of -0.4°C ∼ +0.6°C Over a 0°C to 90°C Range.P. Chen, C. Chen, Y. Peng, K. Wang, and Y. Wang. IEEE J. Solid State Circuits, 45 (3): 600-609 (2010)A 10-bit 1026-Channel Column Driver IC With Partially Segmented Piecewise Linear Digital-to-Analog Converters for UHD TFT-LCDs With One Billion Color Display.C. Lu, P. Lee, Y. Chang, X. Huang, J. Cheng, P. Tseng, C. Chou, P. Chen, T. Chang, and J. Liu. IEEE J. Solid State Circuits, 54 (10): 2703-2716 (2019)A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution.P. Chen, and S. Liu. CICC, page 605-608. IEEE, (1999)Editorial.K. Chakrabarty, M. Alioto, B. Baas, C. Boon, M. Chang, N. Chang, Y. Chang, C. Chang, S. Chang, P. Chen and 35 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 25 (1): 1-20 (2017)An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC.H. Kuo, C. Lu, and P. Chen. IEEE Access, (2021)

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Disambiguation of "Chen, Poki"

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A wide-range and fast-locking clock synthesizer IP based on delay-locked loop.

Please choose a person to relate this publication to

Arno Pokiser

Peter Pokinskyj

Chen Chen

Chen Chen

Shih Chen Chen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chen, Poki"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A wide-range and fast-locking clock synthesizer IP based on delay-locked loop.

Please choose a person to relate this publication to

Arno Pokiser

Peter Pokinskyj

Chen Chen

Chen Chen

Shih Chen Chen

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A wide-range and fast-locking clock synthesizer IP based on delay-locked loop.