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A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors., , , and . VLSI-SoC (Selected Papers), volume 586 of IFIP Advances in Information and Communication Technology, page 307-322. Springer, (2019)Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (5): 2028-2036 (May 2023)GMS: Generic memristive structure for non-volatile FPGAs., , , , and . VLSI-SoC, page 94-98. IEEE, (2012)3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs., , , , and . VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 279-300. Springer, (2020)Improving LUT-based optimization for ASICs., , , , , , and . DAC, page 421-426. ACM, (2022)Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only)., , , , and . FPGA, page 262. ACM, (2015)GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment., , , , , , and . MICRO, page 334-346. ACM, (2019)Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors., and . VLSI-SoC, page 107-112. IEEE, (2018)A high-performance low-power near-Vt RRAM-based FPGA., , and . FPT, page 207-214. IEEE, (2014)Multiple Independent Gate FETs: How many gates do we need?, , , , and . ASP-DAC, page 243-248. IEEE, (2015)