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Disambiguation of "Possani, Vinicius"

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Improving LUT-based optimization for ASICs.

, , , , , , and . DAC, page 421-426. ACM, (2022)

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Vinícius Liebel

Vinícius Maran

Vinicius Malatesta

Vinicius Mariano Carvalho

Vinicius Kannen Cardoso

 

Other publications of authors with the same name

Improving LUT-based optimization for ASICs., , , , , , and . DAC, page 421-426. ACM, (2022)Performance evaluation of optimized transistor networks built using independent-gate FinFET., , , , and . LASCAS, page 227-230. IEEE, (2016)Graph-Based Transistor Network Generation Method for Supergate Design., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 692-705 (2016)Efficient transistor-level design of CMOS gates., , , , , and . ACM Great Lakes Symposium on VLSI, page 191-196. ACM, (2013)Transistor Count Optimization in IG FinFET Network Design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (9): 1483-1496 (2017)Exact Benchmark Circuits for Logic Synthesis., , , , , , and . IEEE Des. Test, 37 (3): 51-58 (2020)SAT-Sweeping Enhanced for Logic Synthesis., , , , , , , , and . DAC, page 1-6. IEEE, (2020)Unlocking fine-grain parallelism for AIG rewriting., , , , , and . ICCAD, page 87. ACM, (2018)NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements., , , , , and . SBCCI, page 1-6. IEEE, (2012)Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation., , , , , and . SBCCI, page 1-6. IEEE, (2018)