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A fast and accurate methodology for power estimation and reduction of programmable architectures.

, , , and . DATE, page 1054-1055. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture., , , , and . DATE, page 531-534. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study., , , and . DSD, page 390-397. IEEE Computer Society, (2009)Designing processors using MAsS, a modular and lightweight instruction-level exploration tool., , , and . DASIP, page 150-155. IEEE, (2011)A Compilation Framework for a Dynamically Reconfigurable Architecture., , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 1058-1067. Springer, (2002)When processors get old: Evaluation of BTI and HCI effects on performance and reliability., , , and . IOLTS, page 185-186. IEEE, (2013)Synchronous Reactive Fine Grain Tasks Management for Homogeneous Many-Core Architectures., , , , and . ARCS Workshops, VDE-Verlag, (2011)ARTM: a lightweight fork-join framework for many-core embedded systems., , , and . DATE, page 1510-1515. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Representing Knowledge for Planning Multisentential Text., and . ANLP, page 203-204. ACL, (1994)A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals., , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 51-62. Kluwer, (2001)Impact of power management on temperature and reliability evolution for an embedded many-core architecture., , , and . ARCS Workshops, VDE-Verlag, (2011)