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FPGA implementation of high speed XTS-AES for data storage devices., , , , , and . ICITST, page 25-28. IEEE, (2011)A Hardware-Efficient Implementation of CLOC for On-chip Authenticated Encryption., , , and . ISVLSI, page 311-315. IEEE Computer Society, (2018)Tight Security of TNT and Beyond: Attacks, Proofs and Possibilities for the Cascaded LRW Paradigm., , , and . IACR Cryptol. ePrint Arch., (2023)Context-Committing Security of Leveled Leakage-Resilient AEAD., , , , , and . IACR Trans. Symmetric Cryptol., 2024 (2): 348-370 (2024)New polynomial basis versatile multiplier over GF(2m) for low-power on-chip crypto-systems., and . ISCAS, page 1438-1441. IEEE, (2015)Crack me if you can: hardware acceleration bridging the gap between practical and theoretical cryptanalysis?: a Survey., , , and . SAMOS, page 167-172. ACM, (2018)Tight Security of TNT and Beyond - Attacks, Proofs and Possibilities for the Cascaded LRW Paradigm., , , and . EUROCRYPT (1), volume 14651 of Lecture Notes in Computer Science, page 249-279. Springer, (2024)SoK: On DFA Vulnerabilities of Substitution-Permutation Networks., , , , , and . AsiaCCS, page 403-414. ACM, (2019)On Hardware Implementation of Tang-Maitra Boolean Functions., , , and . WAIFI, volume 11321 of Lecture Notes in Computer Science, page 111-127. Springer, (2018)Hardware Implementation of Masked SKINNY SBox with Application to AEAD., and . SPACE, volume 13783 of Lecture Notes in Computer Science, page 50-69. Springer, (2022)