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Three-Input Gates for Logic Synthesis., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (10): 2184-2188 (2021)Design and Automation for Quantum Computation and Quantum Technologies., , , и . IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (3): 581-583 (2022)A Resource Estimation and Verification Workflow in Q# Special session paper., , , , и . DATE, стр. 1050-1055. IEEE, (2021)On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis., , , , и . DATE, стр. 1649-1654. IEEE, (2019)Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications., , , и . DAC, стр. 74. ACM, (2019)Mapping NCV Circuits to Optimized Clifford+T Circuits., , и . RC, том 8507 из Lecture Notes in Computer Science, стр. 163-175. Springer, (2014)LUT-Based Hierarchical Reversible Logic Synthesis., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (9): 1675-1688 (2019)A Hybrid Method for Spectral Translation Equivalent Boolean Functions., , и . PACRIM, стр. 1-6. IEEE, (2019)Reversible Pebble Games for Reducing Qubits in Hierarchical Quantum Circuit Synthesis., , , , и . ISMVL, стр. 102-107. IEEE, (2019)Formal Specification Level., , и . FDL (Selected Papers), том 265 из Lecture Notes in Electrical Engineering, стр. 37-52. Springer, (2012)