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Disambiguation of "Madoglio, Paolo"

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A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS.

, , and . ISSCC, page 226-227. IEEE, (2009)

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Giordano Paolo

Paolo Bavaj

Paolo Fornara

Paolo Molteni

Paolo Pedri

 

Other publications of authors with the same name

Transformer-Combining Digital PA with Efficiency Peaking at 0, -6, and -12 dB Backoff in 32nm CMOS., , , , , and . ISCAS, page 1-4. IEEE, (2020)A digital fractional-N PLL with a 3mW 0.004mm2 6-bit PVT and mismatch insensitive TDC., , , , , , and . ESSCIRC, page 193-196. IEEE, (2012)A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving., , , , , , and . IEEE J. Solid State Circuits, 45 (7): 1410-1420 (2010)A Cellular Multiband DTC-Based Digital Polar Transmitter With -153-dBc/Hz Noise in 14-nm FinFET., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 55 (7): 1830-1841 (2020)A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique., , , , , , , and . IEEE J. Solid State Circuits, 48 (7): 1721-1729 (2013)A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS., , and . IEEE J. Solid State Circuits, 44 (12): 3422-3433 (2009)A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS., , , , , , , , , and 2 other author(s). ISSCC, page 168-170. IEEE, (2012)A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving., , , , , , and . ESSCIRC, page 152-155. IEEE, (2009)A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS., , and . ISSCC, page 226-227. IEEE, (2009)A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management., , , , and . ISSCC, page 352-354. IEEE, (2012)