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Compiler-Directed Early Load-Address Generation.

, , and . MICRO, page 138-147. ACM/IEEE Computer Society, (1998)

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Hardware Support for Dynamic Management of Compiler-Directed Computation Reuse., , , and . ASPLOS, page 222-233. ACM Press, (2000)Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results., , , and . HPCA, page 84-93. IEEE Computer Society, (1997)Compiler-Directed Early Load-Address Generation., , and . MICRO, page 138-147. ACM/IEEE Computer Society, (1998)Architecture., and . The VLSI Handbook, CRC Press, (1999)Compiler-Directed Content-Aware Prefetching for Dynamic Data Structures., , and . IEEE PACT, page 91-100. IEEE Computer Society, (2003)Phase-Guided Small-Sample Simulation., , and . ISPASS, page 84-93. IEEE Computer Society, (2007)Optimization for the Intel® Itanium ®Architectur Register Stack., , , and . CGO, page 115-124. IEEE Computer Society, (2003)An Adaptive Fault-Tolerant Memory System for FPGA-based Architectures in the Space Environment., , , , and . AHS, page 250-257. IEEE Computer Society, (2007)Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance., , , , and . DSN, page 297-306. IEEE Computer Society, (2007)Eliminating Dynamic Computation Redundancy. University of Illinois Urbana-Champaign, USA, (2000)