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Disambiguation of "Peltenburg, Johan"

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An Intermediate Representation for Composable Typed Streaming Dataflow Designs.

, , , , , , and . VLDB Workshops, volume 3462 of CEUR Workshop Proceedings, CEUR-WS.org, (2023)

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Johan Waern

Johan Schloemann

Johan Verink

Johan Setianto

Johan Vanparys

 

Other publications of authors with the same name

Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow., , , , , and . FPL, page 270-277. IEEE, (2019)An Intermediate Representation for Composable Typed Streaming Dataflow Designs., , , , , , and . VLDB Workshops, volume 3462 of CEUR Workshop Proceedings, CEUR-WS.org, (2023)Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow., , , , and . ARC, volume 11444 of Lecture Notes in Computer Science, page 32-47. Springer, (2019)Methods for Efficient Integration of FPGA Accelerators with Big Data Systems.. Delft University of Technology, Netherlands, (2020)base-search.net (fttudelft:oai:tudelft.nl:uuid:51989f8f-f672-4f4b-a059-86233869ff47).Tydi-lang: A Language for Typed Streaming Hardware., , , , , , and . SC Workshops, page 520-529. ACM, (2023)Tydi: An Open Specification for Complex Data Structures Over Hardware Streams., , , , and . IEEE Micro, 40 (4): 120-130 (2020)Maximizing systolic array efficiency to accelerate the PairHMM Forward Algorithm., , and . BIBM, page 758-762. IEEE Computer Society, (2016)Tens of gigabytes per second JSON-to-Arrow conversion with FPGA accelerators., , , , and . FPT, page 1-9. IEEE, (2021)Pushing Big Data into Accelerators: Can the JVM Saturate Our Hardware?, , and . ISC Workshops, volume 10524 of Lecture Notes in Computer Science, page 220-236. Springer, (2017)Battling the CPU Bottleneck in Apache Parquet to Arrow Conversion Using FPGA., , , , , and . FPT, page 281-286. IEEE, (2020)