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Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications.

, and . ISCAS, IEEE, (2006)

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Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits., and . ISCAS (1), page 297-300. IEEE, (2003)Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits., , , and . VLSI-DAT, page 1-4. IEEE, (2013)Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process., and . VLSI-DAT, page 1-4. IEEE, (2013)New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process., and . VLSI-DAT, page 1-4. IEEE, (2012)Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology., and . SoCC, page 33-36. IEEE, (2013)A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process., and . IEEE Trans. Biomed. Circuits Syst., 10 (6): 1087-1099 (2016)Electrostatic discharge protection circuits in CMOS IC's using the lateral SCR devices: an overview.. ICECS, page 325-328. IEEE, (1998)Design of Multi-Channel Monopolar Biphasic Stimulator for Implantable Biomedical Applications., and . MWSCAS, page 1-4. IEEE, (2018)Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS., and . CICC, page 689-696. IEEE, (2009)Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices., and . CICC, page 539-542. IEEE, (2009)