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A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels., , , and . Journal of Circuits, Systems, and Computers, 14 (4): 877-893 (2005)Mapping DSP applications on processor/coarse-grain reconfigurable array architectures., , and . ISCAS, IEEE, (2006)Resource constrained modulo scheduling for coarse-grained reconfigurable arrays., , and . ISCAS, IEEE, (2006)Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware., , and . IPDPS, IEEE, (2006)A Novel Data-Path for Accelerating DSP Kernels., , , , and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 363-372. Springer, (2004)High-speed hardware implementations of the KASUMI block cipher., , and . ISCAS (2), page 549-552. IEEE, (2004)A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures., , and . IPDPS, IEEE Computer Society, (2005)A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher., , and . ISCAS (5), page 4641-4644. IEEE, (2005)A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms., , , , and . DATE, page 247-252. IEEE Computer Society, (2004)Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-Path., , and . ICSAMOS, page 85-92. IEEE, (2006)