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Disambiguation of "Kim, Woo-Seop"

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8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology.

, , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 45 (1): 111-119 (2010)

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Wan-Seop Kim

Jin-Seop Kim

Jong-Woo Kim

Woo-Sun Kim

Jong-Woo Kim

 

Other publications of authors with the same name

Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module., , , , , , , and . SoCC, page 343-348. IEEE, (2013)An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme., , , , , , , , , and 9 other author(s). ISSCC, page 527-536. IEEE, (2006)A control network architecture based on EIA-709.1 protocol for power line data communications., , , , and . IEEE Trans. Consumer Electronics, 48 (3): 650-655 (2002)BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 44 (11): 2987-2998 (2009)A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 45 (4): 880-888 (2010)A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter., , , , , , and . IEEE J. Solid State Circuits, 41 (1): 127-134 (2006)A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW., , , , , , , , , and 19 other author(s). ISSCC, page 498-500. IEEE, (2011)