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A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS.

X. Sun, A. Boora, W. Zhang, V. Pamula, and V. Sathe. ISSCC, page 230-232. IEEE, (2019)

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Madan Sathe

Saket Sathe

Nita Sathe-Meis

Richard Satherley

Other publications of authors with the same name

A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS.J. Uehlin, W. Smith, V. Pamula, E. Pepin, S. Perlmutter, V. Sathe, and J. Rudell. IEEE J. Solid State Circuits, 55 (7): 1749-1761 (2020)CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration.S. Gudaparthi, S. Singh, S. Narayanan, R. Balasubramonian, and V. Sathe. HPCA, page 876-891. IEEE, (2022)Exploring computation-communication tradeoffs in camera systems.A. Mazumdar, T. Moreau, S. Kim, M. Cowan, A. Alaghi, L. Ceze, M. Oskin, and V. Sathe. IISWC, page 177-186. IEEE Computer Society, (2017)Quasi-Resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking System for Dynamic Voltage-Frequency Scaling Systems.F. Rahman, and V. Sathe. IEEE J. Solid State Circuits, 53 (3): 924-935 (2018)Regenerative Breaking: Recovering Stored Energy from Inactive Voltage Domains for Energy-efficient Systems-on-Chip.A. Najafi, J. Rudell, and V. Sathe. ISLPED, page 94-99. ACM, (2016)A Reconfigurable Digital Beamforming V-Band Phased-Array Receiver.D. Dosluoglu, K. Chu, D. Peña-Colaiocco, I. Zhao, V. Sathe, and J. Rudell. ESSCIRC, page 493-496. IEEE, (2022)Tutorial 4A: Supply voltage noise and mitigation for real world SoCs.V. Sathe, and A. Marshall. SoCC, page 1-3. IEEE, (2016)A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS.X. Sun, A. Boora, W. Zhang, V. Pamula, and V. Sathe. ISSCC, page 230-232. IEEE, (2019)Bandwidth Extension on Raw Audio via Generative Adversarial Networks.S. Kim, and V. Sathe. CoRR, (2019)MATIC: Learning around errors for efficient low-voltage neural network accelerators.S. Kim, P. Howe, T. Moreau, A. Alaghi, L. Ceze, and V. Sathe. DATE, page 1-6. IEEE, (2018)

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Disambiguation of "Sathe, Visvesh"

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A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS.

Please choose a person to relate this publication to

Madan Sathe

Saket Sathe

Nita Sathe-Meis

Richard Satherley

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sathe, Visvesh"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS.

Please choose a person to relate this publication to

Madan Sathe

Saket Sathe

Nita Sathe-Meis

Richard Satherley

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS.